標題: Two systolic architectures for modular multiplication
作者: Tsai, WC
Shung, CB
Wang, SJ
交大名義發表
National Chiao Tung University
關鍵字: cryptosystems;montgomery;RSA;systolic
公開日期: 1-二月-2000
摘要: This article presents two systolic architectures to speed up the computation of modular multiplication in RSA cryptosystems. In the double-layer architecture, the main operation of Montgomery's algorithm is partitioned into two parallel operations after using the precomputation of the quotient bit. In the non-interlaced architecture, we eliminate the one-clock-cycle gap between iterations by pairing off the double-layer architecture. We compare our architectures with some previously proposed Montgomery-based systolic architectures, on the basis of both modular multiplication and modular exponentiation. The comparisons indicate that our architectures offer the highest speed, lower hardware complexity, and lower power consumption.
URI: http://dx.doi.org/10.1109/92.820767
http://hdl.handle.net/11536/30741
ISSN: 1063-8210
DOI: 10.1109/92.820767
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 8
Issue: 1
起始頁: 103
結束頁: 107
顯示於類別:期刊論文


文件中的檔案:

  1. 000085569400012.pdf