標題: Implementation of Petri nets using a field-programmable gate array
作者: Yang, SK
Liu, TS
機械工程學系
Department of Mechanical Engineering
關鍵字: Petri net implementation;FPGA;preventive maintenance;logic circuit;ASIC
公開日期: 1-三月-2000
摘要: Although Petri nets have various capabilities, the Petri net approach is done on paper. A field-programmable gate array (FPGA) is implemented in this study so as to realize basic Petri net symbols, logic structures in Petri nets, and specific functions for Petri nets by logic circuits. As an example, a Petri net for an early failure detection and isolation arrangement (EFDIA) is implemented as an application-specific integrated circuit (ASIC) on a Xilinx Demonstration Board. This ASIC is verified by three simulations dealing with three different failure scenarios of a system, and the ASIC functions identically to the EFDIA Petri net. Accordingly not only the EFDIA Petri net but also any specific function Petri nets can be implemented by FPGA circuits. Copyright (C) 2000 John Wiley & Sons, Ltd.
URI: http://hdl.handle.net/11536/30692
http://dx.doi.org/10.1002/(SICI)1099-1638(200003/04)16:2<99
ISSN: 0748-8017
DOI: 10.1002/(SICI)1099-1638(200003/04)16:2<99
期刊: QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL
Volume: 16
Issue: 2
起始頁: 99
結束頁: 116
顯示於類別:期刊論文


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  1. 000086796700004.pdf