標題: A High-Speed Real-Time Binary BCH Decoder
作者: Wei, Shyue-Win
Wei, Che-Ho
電子工程學系及電子研究所
電信研究中心
Department of Electronics Engineering and Institute of Electronics
Center for Telecommunications Research
關鍵字: BCH code;error-control coding;real-time implementation;VLSI architecture
公開日期: 1-Apr-1993
摘要: A high-speed real-time decoder for t-error-correcting binary Bose-Chaudhuri-Hocquenghem (BCH) codes based on a modified step-by-step decoding algorithm is presented. The average operation cycles for decoding each received word is just equal to the block length of the codeword. The decoder is constructed by three modules: the syndrome module, the comparison module, and the error corrector. Since all of the modules can be implemented by systolic circuits, the operation data rate of this decoder can theoretically be up to a rate of the inverse of two logic-gate delays. Based on different VLSI technologies, such as CMOS, BiCMOS and Gab, the decoder can be operated from approximately several hundreds megabits per second to the order of gigabits per second. Thus, the decoder can be applied in the broadband service and video processing. Besides, by avoiding the use of inverse operation in the step-by-step decoding method, the circuit complexity of this decoder can be much less than the standard algebraic method in which the inverse operation is usually required for finding the coefficients of the error-location polynomial. The detailed circuit diagrams of the comparison module and error corrector for the double- and triple-error-correcting binary BCH codes are given for illustration.
URI: http://dx.doi.org/10.1109/76.212719
http://hdl.handle.net/11536/3069
ISSN: 1051-8215
DOI: 10.1109/76.212719
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Volume: 3
Issue: 2
起始頁: 138
結束頁: 147
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