標題: Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
作者: Ker, MD
Chang, HH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-三月-2000
摘要: The lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered by noise pulses when the ICs are operated in the application systems. A cascoded design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS ICs without causing unexpected operation errors or latchup danger. The temperature dependence on the holding voltage of the cascoded LVTSCRs has been investigated in detail. From the experimental verification, the cascoded LVTSCRs can be fully turned on within a time below 20 ns. The ESD robustness per layout area of the three-cascoded LVTSCRs can be 0.83 V/mu m(2) in a 0.35-mu m silicide CMOS process without using the extra silicide-blocking and ESD-implant masks, whereas the ESD robustness of the gate-grounded NMOS is only 0.25 V/mu m(2). Such cascoded LVTSCRs with a tunable holding voltage greater than VDD can provide CMOS ICs with effective component-level ESD protection but without causing catchup danger if it is accidentally triggered by the system-level overshooting or undershooting noise pulses. (C) 2000 Elsevier Science Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/S0038-1101(99)00247-6
http://hdl.handle.net/11536/30667
ISSN: 0038-1101
DOI: 10.1016/S0038-1101(99)00247-6
期刊: SOLID-STATE ELECTRONICS
Volume: 44
Issue: 3
起始頁: 425
結束頁: 445
顯示於類別:期刊論文


文件中的檔案:

  1. 000085469300006.pdf