標題: A simple processor core design for DCT/IDCT
作者: Chang, TS
Kung, CS
Jen, CW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: DCT/IDCT;H.263;processor
公開日期: 1-四月-2000
摘要: This paper presents a cost effective processor core design that features the simplest hardware and is suitable for discrete cosine transform/indiscrete cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two dimensional DCT algorithm, the bit-level adder-based distributed arithmetic, and common subexpression sharing;to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easily scaled for higher throughput rate requirements. The DCT design has been implemented by 0.6 mu m SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm(2), The proposed design can meet real-time DCT/IDCT requirements of H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional computing power for other operations when operating at 33 Mhz.
URI: http://dx.doi.org/10.1109/76.836290
http://hdl.handle.net/11536/30625
ISSN: 1051-8215
DOI: 10.1109/76.836290
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Volume: 10
Issue: 3
起始頁: 439
結束頁: 447
顯示於類別:期刊論文


文件中的檔案:

  1. 000086613300013.pdf