標題: AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY
作者: SHUNG, CB
LIN, HD
CYPHER, R
SIEGEL, PH
THAPAR, HK
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-四月-1993
摘要: The Viterbi algorithm has been widely applied to many decoding and estimation applications in communications and signal processing. A state-parallel implementation is usually used in which one add-compare-select (ACS) unit is devoted to each state in the trellis. In this paper we present a systematic approach of partitioning, scheduling, and mapping the N trellis states to P ACS's, where N > P. The area saving of our architecture comes from the reduced number of both the ACS's and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the area-efficient architecture offers a favorable (smaller) area-time product, compared to a state-parallel implementation. These results will be demonstrated by application examples in the accompanying paper.
URI: http://dx.doi.org/10.1109/26.223789
http://hdl.handle.net/11536/3060
ISSN: 0090-6778
DOI: 10.1109/26.223789
期刊: IEEE TRANSACTIONS ON COMMUNICATIONS
Volume: 41
Issue: 4
起始頁: 636
結束頁: 644
顯示於類別:期刊論文


文件中的檔案:

  1. A1993LP11800018.pdf