標題: An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits
作者: Wong, SC
Lee, TGY
Ma, DJ
Chao, CJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: closed-form models;crossover capacitance;multilevel interconnects;VLSI circuits
公開日期: 1-May-2000
摘要: We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 mu m and wire thickness down to 0.15 mu m. The model is useful for VLSI design and process optimization.
URI: http://dx.doi.org/10.1109/66.843637
http://hdl.handle.net/11536/30551
ISSN: 0894-6507
DOI: 10.1109/66.843637
期刊: IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
Volume: 13
Issue: 2
起始頁: 219
結束頁: 227
Appears in Collections:Conferences Paper


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