標題: OPTIMAL TILE PARTITION FOR SPACE REGION OF INTEGRATED-CIRCUITS GEOMETRY
作者: HSIAO, PY
LIN, CY
SHEW, PW
資訊工程學系
Department of Computer Science
關鍵字: VLSI LAYOUT;CHANNEL PARTITION;CORNER STITCHING;TILE GENERATION
公開日期: 1-五月-1993
摘要: An optimal tile partition (OTP) is presented for partitioning the space region of a VLSI layout plane into rectangular space tiles. It modifies the corner stitching data structure to optimise the space tile partition. There is a serious restriction in the original corner stitching data structure, i.e. the solid rectangles cannot overlap each other, whereas our OTP allows overlapping. This paper also shows three theorems with rigorous proofs and experimental results to obtain the minimal number of the space tiles through the OTP. Moreover, a dynamic plane-sweep algorithm based on region query for the OTP has been developed. Using the OTP, the memory efficiency and the local query operations of the original corner stitching data structure have been enhanced.
URI: http://hdl.handle.net/11536/3032
ISSN: 0143-7062
期刊: IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES
Volume: 140
Issue: 3
起始頁: 145
結束頁: 153
顯示於類別:期刊論文


文件中的檔案:

  1. A1993LW32100001.pdf