標題: AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS
作者: SHUNG, CB
LIN, HD
CYPHER, R
SIEGEL, PH
THAPAR, HK
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-五月-1993
摘要: In the previous paper, we established the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm. In this paper, we will show area-efficient architectures for practical codes to illustrate the design procedures and demonstrate the favorable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes will be presented. We will also discuss the application of our area-efficient techniques to codes with a very large numbers of states, codes with time-varying trellises, and a programmable Viterbi decoder.
URI: http://dx.doi.org/10.1109/26.225495
http://hdl.handle.net/11536/3022
ISSN: 0090-6778
DOI: 10.1109/26.225495
期刊: IEEE TRANSACTIONS ON COMMUNICATIONS
Volume: 41
Issue: 5
起始頁: 802
結束頁: 807
顯示於類別:期刊論文


文件中的檔案:

  1. A1993LR65600020.pdf