|標題:||INTEGRA: Fast Multi-Bit Flip-Flop Clustering for Clock Power Saving Based on Interval Graphs|
|作者:||Jiang, Iris H. -R.|
Tsai, Evan Y. -W.
Chen, Lancer S. -F.
Department of Electronics Engineering and Institute of Electronics
|關鍵字:||Clock power;multi-bit flip-flops;post-placement optimization;interval graph;coordinate transformation|
|摘要:||Clock power is the major contributor to dynamic power for modern IC design. A conventional single-bit; flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering such cells and forming a multi-bit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, even can save the clock network power and facilitate the skew control. Hence, in this paper, we focus on multi-bit flip-flop clustering at post-placement to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-size sequences as our representation. Without enumerating all compatible combinations, we extract only partial sequences that are necessary to cluster flip-flops at a time, thus leading to an efficient clustering scheme. Moreover, our coordinate transformation brings fast; operations to execute our algorithm. Experimental results show the superior efficiency and effectiveness of our algorithm.|
|期刊:||ISPD 11: PROCEEDINGS OF THE 2011 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN|
|Appears in Collections:||Conferences Paper|