標題: High-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel
作者: Chang, SJ
Chang, CY
Chen, CM
Chao, TS
Lee, YJ
Huang, TY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: DTMOS;indium;super-steep retrograde (SSR) channel
公開日期: 1-十二月-2000
摘要: In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In-SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V-th in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS, As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 muA/mum (off-state current 40 nA/mum), a record-high Gm = 1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.
URI: http://dx.doi.org/10.1109/16.887025
http://hdl.handle.net/11536/30075
ISSN: 0018-9383
DOI: 10.1109/16.887025
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 47
Issue: 12
起始頁: 2379
結束頁: 2384
顯示於類別:期刊論文


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  1. 000165561900022.pdf