標題: ANALYTICAL DESIGN FORMULATION FOR MINORITY-CARRIER WELL-TYPE GUARD RINGS IN CMOS CIRCUITS
作者: CHEN, MJ
HUANG, CY
TSENG, PN
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: CMOS CIRCUITS;GUARD RINGS;DUAL COLLECTOR STRUCTURES
公開日期: 1-六月-1993
摘要: Minority carriers injected from an active emitter into the substrate and partially collected by the bottom well junction in an epitaxial CMOS structure are studied. Two-dimensional numerical simulation has revealed that the minority-carrier collection current along the bottom well junction is contributed primarily by two mechanisms: the first due to minority carriers injected into a layer between the upper collecting plate and the bottom reflecting plate; and the second due to those penetrating the high/low junction and then spreading out in the large, highly-doped bulk as in the nonepitaxial case. Based on this observation, a new analytic model for the minority-carrier escape current has been developed as a measure of well-type guard ring efficiency. This model, including a closed-form expression as function of epitaxial layer thickness, well junction depth and guard ring width, has been confirmed by experimental data as well as by two-dimensional numerical simulation. As predicted by the model, the measured escape current has been found to be dominated by the second mechanism for the case of well junction depth close to epitaxial layer thickness while the first mechanism has been identified to dominate the escape current measured from the structure having sufficient epitaxial layer thicknesses.
URI: http://hdl.handle.net/11536/2999
ISSN: 0956-3768
期刊: IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS
Volume: 140
Issue: 3
起始頁: 182
結束頁: 186
顯示於類別:期刊論文


文件中的檔案:

  1. A1993LN28800007.pdf