標題: On-chip ESD protection design by using polysilicon diodes in CMOS process
作者: Ker, MD
Chen, TY
Wang, TH
Wu, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: electrostatic discharge (ESD);ESD protection circuit;polysilicon diode;smart card;transmission-line-pulse (TLP) generator
公開日期: 1-四月-2001
摘要: A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is first proposed in this paper, Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-pulse (TLP) generator to investigate its ESD robustness, Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original similar to 300 V to become greater than or equal to3 kV, This design has been practically applied in a mass-production smart-card IC.
URI: http://dx.doi.org/10.1109/4.913746
http://hdl.handle.net/11536/29724
ISSN: 0018-9200
DOI: 10.1109/4.913746
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 36
Issue: 4
起始頁: 676
結束頁: 686
顯示於類別:期刊論文


文件中的檔案:

  1. 000167873300012.pdf