標題: High-bandwidth x86 instruction fetching based on instruction pointer table
作者: Chiu, JC
Chung, CP
資訊工程學系
Department of Computer Science
公開日期: 1-五月-2001
摘要: Providing higher degree superscalar instruction fetching is a major concern in a high performance superscalar processor design. In x86 architectures, the variable-length instructions make fetching multiple instructions in a cycle difficult. A common practice is to use predecoded information to help in instruction fetching, while the complex instruction formats induce high redundancies in storing and processing the pre-decoded information in the cache. In the paper, the authors propose to use an Instruction Identifier to predict instruction length and store the instruction pointers as superscalar instruction group indicators. With this method, the difficulty of achieving a high instruction fetch degree (>3) can be overcome. Simulation results suggest that the Instruction Identifier with a 64-entry table is a good performance/cost choice. In the meantime, as the table size decreases, the prediction scheme becomes increasingly important. Moreover, simulation and circuit synthesis show that this design is feasible for high clock rate design.
URI: http://dx.doi.org/10.1049/ip-cdt:20010456
http://hdl.handle.net/11536/29684
ISSN: 1350-2387
DOI: 10.1049/ip-cdt:20010456
期刊: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Volume: 148
Issue: 3
起始頁: 113
結束頁: 118
顯示於類別:期刊論文


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  1. 000170427200002.pdf