|標題:||ESD protection under grounded-up bond pads in 0.13 mu m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology|
Department of Electronics Engineering and Institute of Electronics
|關鍵字:||copper metal;die cracking;ESD;fluorinated silicate glass;FSG;IMD;intermetal dielectric;low-k;stress mismatch;wire bonding|
|摘要:||Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 mum full eight-level copper metal CMOS process technology with fluorinated silicate glass (FSG) low-k intermetal dielectric (IMD). The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point (V-t2, I-t2). High current I-V measured from the different level metal layers stack structures shows that 1) I-t2 depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) V-t2 increases with the number of metal layers. The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device. Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications.|
|期刊:||IEEE ELECTRON DEVICE LETTERS|
|Appears in Collections:||Articles|
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