標題: Aggressive scheduling for memory accesses of CISC superscalar microprocessors
作者: Shiu, RM
Hwang, HY
Shann, JJJ
資訊工程學系
Department of Computer Science
關鍵字: CISC;superscalar;memory access ordering;x86 microprocessor;load bypassing;load forwarding
公開日期: 1-Sep-2001
摘要: For CISC microprocessors, the proportion of memory access instructions is relatively high, and a specific address is likely to be accessed repeatedly in a short period of time because of register-to-memory or memory-to-memory instruction set architectures and limited register sets. As superscalar architectures advance, an aggressive scheduling policy for memory access becomes crucial. In this paper, we examine the scheduling policies of loads/stores on CISC superscalar processors and develop an aggressive scheduling policy called preload. The preload scheduling policy allows loads to precede the earlier unsolved pending stores, and delays the checking of conflict and forwarding of data until the data is loaded, thereby allowing greater tolerance of the latency for address generation. Because of its popularity, we focus our attention on the x86 instruction set. Simulation results show that the preload achieves a higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the preload can achieve even higher performance.
URI: http://hdl.handle.net/11536/29446
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 17
Issue: 5
起始頁: 787
結束頁: 803
Appears in Collections:Articles