標題: Speed up of rendering pipeline by deferred lighting and triple queue structure
作者: Liang, BS
Jen, CW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 25-Oct-2001
摘要: Redundant operations and stalls prevent a rendering pipeline from full-speed operation. To speed up the rendering pipeline, a triple queue structure is proposed to smooth the pipeline and to obtain benefit from deferred lighting. The results of cycle-accurate simulation show that the proposed structure can reduce rendering cycles to 52.9% in small size queues.
URI: http://dx.doi.org/10.1049/el:20010901
http://hdl.handle.net/11536/29335
ISSN: 0013-5194
DOI: 10.1049/el:20010901
期刊: ELECTRONICS LETTERS
Volume: 37
Issue: 22
起始頁: 1332
結束頁: 1333
Appears in Collections:Articles


Files in This Item:

  1. 000171943100011.pdf