標題: Edge hole direct Tunneling leakage in ultrathin gate oxide p-channel MOSFETs
作者: Yang, KN
Huang, HT
Chen, MJ
Lin, YM
Yu, MC
Jang, SSM
Yu, DCH
Liang, MS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: direct tunneling (DT);edge direct tunneling (EDT);gate-induced drain leakage (GIDL);MOSFETs;oxide;surface quantization;valence-band electron tunneling (VBET)
公開日期: 1-Dec-2001
摘要: This paper examines the edge direct tunneling (EDT) of holes from p(+) polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T-OX = 1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E-OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E-OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E-OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected.
URI: http://dx.doi.org/10.1109/16.974705
http://hdl.handle.net/11536/29206
ISSN: 0018-9383
DOI: 10.1109/16.974705
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 48
Issue: 12
起始頁: 2790
結束頁: 2795
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