標題: AN AREA-EFFICIENT MEDIAN FILTERING IC FOR IMAGE VIDEO APPLICATIONS
作者: HSIEH, PW
TSAI, JM
LEE, CY
電控工程研究所
Institute of Electrical and Control Engineering
公開日期: 1-八月-1993
摘要: An area efficient IC for high-throughput median filtering applications is presented in this paper. This IC implements a modified delete-and-insert sorting algorithm which is very efficient for running order statistics applications. In hardware design, we first map the algorithm onto a regular PE structure, where each PE consistis of shift register, comparator, and some control gates. Then we conduct full-custom circuit/layout design of the PE to meet performance requirement. A proto-type chip for 64 input samples is implemented and tested. Results show that clock rate up to 50 MHz can be achieved using a 1.2 mum CMOS double metal technology. Two outstanding features of this IC are: (1) any specified order of input patterns can be produced within one clock cycle; (2) each chip can handle at most 64 data and can be cascaded as the number of sorted data is over 64. Thus this IC releases the bottle-neck of median search in hardware realization for many system designs, making real-time performance achievable.
URI: http://dx.doi.org/10.1109/30.234627
http://hdl.handle.net/11536/2913
ISSN: 0098-3063
DOI: 10.1109/30.234627
期刊: IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
Volume: 39
Issue: 3
起始頁: 504
結束頁: 509
顯示於類別:期刊論文


文件中的檔案:

  1. A1993LY44600053.pdf