標題: A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation
作者: Li, Y
Sze, SM
Chao, TS
電子工程學系及電子研究所
友訊交大聯合研發中心
Department of Electronics Engineering and Institute of Electronics
D Link NCTU Joint Res Ctr
關鍵字: DTMOS;dynamic domain decomposition;linux cluster;load balancing;MOSFET;parallel I-V;points calculation;VLSI device simulation
公開日期: 2002
摘要: We present a new parallel semiconductor device simulation using the dynamic load balancing approach. This semiconductor device simulation based on the adaptive finite volume method with a posteriori error estimation has been developed and successfully implemented on a 16-PC Linux cluster with a message passing interface library. A constructive monotone iterative technique is also applied for solution of the system of nonlinear algebraic equations. Two different parallel versions of the algorithm to perform a complete device simulation are proposed. The first is a dynamic parallel domain decomposition approach, and the second is a parallel current-voltage characteristic points simulation. This implementation shows that a well-designed load balancing simulation can significantly reduce the execution time up to an order of magnitude. Compared with the measured data, numerical results on various submicron VLSI devices are presented, to show the accuracy and efficiency of the method.
URI: http://hdl.handle.net/11536/29116
http://dx.doi.org/10.1007/s003660200011
ISSN: 0177-0667
DOI: 10.1007/s003660200011
期刊: ENGINEERING WITH COMPUTERS
Volume: 18
Issue: 2
起始頁: 124
結束頁: 137
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