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dc.contributor.authorWang, HCHen_US
dc.contributor.authorWang, CCen_US
dc.contributor.authorDiaz, CHen_US
dc.contributor.authorLiew, BKen_US
dc.contributor.authorSun, JYCen_US
dc.contributor.authorWang, THen_US
dc.date.accessioned2014-12-08T15:42:55Z-
dc.date.available2014-12-08T15:42:55Z-
dc.date.issued2002-01-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.974751en_US
dc.identifier.urihttp://hdl.handle.net/11536/29085-
dc.description.abstractOptimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFET's with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced as compared to the one without TED. The reason is that the TED effect can yield a more graded n(-) LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric fielden_US
dc.language.isoen_USen_US
dc.subjecthot carriersen_US
dc.subjectMOS devicesen_US
dc.subjecttransient enhanced diffusionen_US
dc.titleArsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devicesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/16.974751en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume49en_US
dc.citation.issue1en_US
dc.citation.spage67en_US
dc.citation.epage71en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000173338000012-
dc.citation.woscount3-
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