標題: Analysis of application of the IDDQ technique to the deep sub-micron VLSI testing
作者: Lu, CW
Lee, CL
Su, CC
Chen, JE
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: IDDQ testing;deep sub-micron;VLSI
公開日期: 1-Feb-2002
摘要: In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 x 10(7) gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.
URI: http://dx.doi.org/10.1023/A:1013784124552
http://hdl.handle.net/11536/29058
ISSN: 0923-8174
DOI: 10.1023/A:1013784124552
期刊: JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
Volume: 18
Issue: 1
起始頁: 89
結束頁: 97
Appears in Collections:Conferences Paper


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