標題: Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
作者: Ker, Ming-Dou
Yen, Cheng-Cheng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electromagnetic compatibility (EMC);electrostatic discharge (ESD);ESD protection circuit;latchup;system-level ESD test
公開日期: 1-Nov-2008
摘要: On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mu m CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a "latch-on" state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
URI: http://dx.doi.org/10.1109/JSSC.2008.2005451
http://hdl.handle.net/11536/28743
ISSN: 0018-9200
DOI: 10.1109/JSSC.2008.2005451
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 43
Issue: 11
起始頁: 2533
結束頁: 2545
Appears in Collections:Conferences Paper


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