標題: Structural fault based specification reduction for testing analog circuits
作者: Chang, SJ
Lee, CL
Chen, JE
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: analog test;test cost reduction;specification-based test;fault-based test
公開日期: 1-Dec-2002
摘要: Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.
URI: http://dx.doi.org/10.1023/A:1020892721493
http://hdl.handle.net/11536/28372
ISSN: 0923-8174
DOI: 10.1023/A:1020892721493
期刊: JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
Volume: 18
Issue: 6
起始頁: 571
結束頁: 581
Appears in Collections:Articles


Files in This Item:

  1. 000178932300002.pdf