標題: Automatic interconnection rectification for SoC design verification based on the port order fault model
作者: Wang, CY
Tung, SW
Jou, JY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: automatic interconnection rectification (AIR);characteristic vector (CV);correction;detection;diagnosis;port order fault (POF);system-on-a-chip (SoC);undetected port sequence (UPS);verification
公開日期: 1-Jan-2003
摘要: Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. The experiments are conducted on combinational and sequential benchmarks. Experimental results show that the AIR can correct the misplaced interconnection exactly within reasonable efforts and, therefore, accelerates the integration verification of SoC designs.
URI: http://dx.doi.org/10.1109/TCAD.2002.805723
http://hdl.handle.net/11536/28290
ISSN: 0278-0070
DOI: 10.1109/TCAD.2002.805723
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 22
Issue: 1
起始頁: 104
結束頁: 114
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