標題: Parallel execution of a connected component labeling operation on a linear array architecture
作者: Wang, KB
Chia, TL
Chen, Z
Lou, DC
資訊科學與工程研究所
Institute of Computer Science and Engineering
關鍵字: connected component labeling;parallel algorithm;parallel processing;linear array;processing element
公開日期: 1-Mar-2003
摘要: This work presents a novel parallel algorithm and architecture for finding connected components in an image. Simulation results indicate that the proposed algorithm has an execution time of N-2 +6N-4 cycles for an NxN image using an architecture containing 4 parallel processors. The proposed hardware can process a 128 x 128 image in 0.8574 ms and uses only 4 processors, compared to 0.85 ms and 128 processors for the work of Ranganathan et al. [14], and 94.6 ms and 16384 processors for the MPP [22]. Among the advantages of the novel architecture are modularity, expandability, regular data flow, and simple hardware. These properties are extremely desirable for VLSI implementations. Additionally, the execution time of the algorithm is independent of its image content; thus, it is quite flexible.
URI: http://hdl.handle.net/11536/28057
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 19
Issue: 2
起始頁: 353
結束頁: 370
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