標題: THE BEHAVIOR OF BILATERAL LATCH-UP TRIGGERING IN VLSI ELECTROSTATIC DISCHARGE DAMAGE PROTECTION CIRCUITS
作者: HUANG, HS
CHANG, CY
HSU, CC
CHEN, KL
LIN, JK
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: VLSI;ESD;LATCH-UP;DIAC;SCR AND BILATERAL
公開日期: 1-Nov-1993
摘要: A new latch-up phenomenon that shows symmetrical diac I-V characteristics has been discovered recently. Electrical measurements show that a diac parasitic semiconductor-controlled-rectifier (SCR) device can exist between two adjacent electro static discharge damage (ESD) protection circuits or output buffers. The SCR consists of two parasitic P-N-P-N paths and can easily induce a localized SCR latch-up between two adjacent input or output terminals. This is not similar to traditional latch-up that creates a parasitic P-N-P-N path between power supply and ground pins, but is a new bilateral latch-up path between two adjacent input and output pins. A new latch-up failure mode due to this diac structure, which creates a bilateral path during temperature humidity bias (THB) testing, is discussed. Some suggestions regarding the improvement of this diac latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified diac latch-up lumped element model successfull explains this phenomenon.
URI: http://dx.doi.org/10.1143/JJAP.32.4928
http://hdl.handle.net/11536/2805
ISSN: 0021-4922
DOI: 10.1143/JJAP.32.4928
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
Volume: 32
Issue: 11A
起始頁: 4928
結束頁: 4933
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  1. A1993ML96600013.pdf