標題: Optimization of the anti-punch-through implant for electrostatic discharge protection circuit design
作者: Li, YM
Lee, JW
Sze, SM
電子工程學系及電子研究所
友訊交大聯合研發中心
Department of Electronics Engineering and Institute of Electronics
D Link NCTU Joint Res Ctr
關鍵字: ESD protection device;anti-punch-through implant;electron temperature;2D HD simulation
公開日期: 1-Apr-2003
摘要: In this study, an optimal anti-punch-through implant for electrostatic discharge (ESD) protection devices is investigated. By solving a two-dimensional (2D) hydrodynamic (HD) device model as well as a lattice temperature equation numerically, the current density, carrier temperature, and parasitic capacitance of four different device structures are analyzed and compared for suppressing short-channel effects, reducing device heating, and improving ESD robustness simultaneously. The structure difference among these four devices is the location of anti-punch-through implantation; that is: (a) the Type 1 device is the control device without anti-punch-through implantation; (b) the Type 2 device is the device with anti-punch-through implantation under the source/drain extension; (c) the Type 3 device, with anti-punch-through implantation under the deep source/drain junction; and (d) the Type 4 device, with anti-punch-through implantation surrounding all junctions. By comparing these four device structures, we find that the Type 4 device not only has a lower electron temperature (and hence good thermal immunity) but also has a larger current density under an applied high bias. Therefore, this device maintains a higher driving capacity without producing a higher amount of heat and is suitable for the ESD protection device application.
URI: http://dx.doi.org/10.1143/JJAP.42.2152
http://hdl.handle.net/11536/28019
ISSN: 0021-4922
DOI: 10.1143/JJAP.42.2152
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
Volume: 42
Issue: 4B
起始頁: 2152
結束頁: 2155
Appears in Collections:Conferences Paper