標題: A High-Troughput Radix-4 Log-MAP Decoder With Low Complexity LLR Architecture
作者: Chuang, Hsiang-Tsung
Tseng, Kai-Hsin
Fang, Wai-Chi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm(2) on UMC 0.13 mu m standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.
URI: http://hdl.handle.net/11536/28009
http://dx.doi.org/10.1109/VDAT.2009.5158137
ISBN: 978-1-4244-2781-9
DOI: 10.1109/VDAT.2009.5158137
期刊: 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM
起始頁: 231
結束頁: 234
Appears in Collections:Conferences Paper


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