標題: Corner sequence - A P-admissible floorplan representation with a worst case linear-time packing scheme
作者: Lin, JM
Chang, YW
Lin, SP
資訊工程學系
電子工程學系及電子研究所
Department of Computer Science
Department of Electronics Engineering and Institute of Electronics
關鍵字: floor planning;layout;physical design;placement;VLSI design
公開日期: 1-Aug-2003
摘要: Floorplanning/placement allocates a set of modules into a chip so that no two modules overlap and some specified objective is optimized. To facilitate floorplanning/placement, we need to develop an efficient and effective representation to model the geometric relationship among modules. In this paper, we present a P-admissible representation, called corner sequence (CS), for non-slicing floorplans. CS consists of two tuples that denote the packing sequence of modules and the corners to which the modules are placed. CS is very effective and simple for implementation. Also, it supports incremental update during packing. In particular, it induces a generic worst case linear-time packing scheme that can also be applied to other representations. Experimental results show that CS achieves very promising results for a set of commonly used MCNC benchmark circuits.
URI: http://dx.doi.org/10.1109/TVLSI.2003.816137
http://hdl.handle.net/11536/27675
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2003.816137
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 11
Issue: 4
起始頁: 679
結束頁: 686
Appears in Collections:Articles


Files in This Item:

  1. 000185247100012.pdf