標題: ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness
作者: Ker, MD
Hsu, HC
Peng, JJ
電機學院
College of Electrical and Computer Engineering
關鍵字: electrostatic discharge (ESD);ESD implantation;ESD protection;machine model
公開日期: 1-Oct-2003
摘要: A new electrostatic discharge (ESD) implantation method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 mum/0.5 mum has been successfully improved from the original 450 V to become 675 V in a 0.25-mum CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 mum/0.5 mum for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation Method with the n-type impurity can be fully Merged into the general subquarter-micron CMOS processes.
URI: http://dx.doi.org/10.1109/TED.2003.817273
http://hdl.handle.net/11536/27511
ISSN: 0018-9383
DOI: 10.1109/TED.2003.817273
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 50
Issue: 10
起始頁: 2126
結束頁: 2134
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