標題: A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITS
作者: HUANG, HS
CHANG, CY
CHEN, KL
LIU, IO
HSU, CC
LIN, JK
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: VLSI;CMOS;OUTPUT BUFFER;LATCH-UP;DIAC;SCR;BILATERAL
公開日期: 1-Jan-1994
摘要: The results of serial studies on the behavior of bilateral latch-up in complementary metal-oxide-semiconductor field effect transistor (CMOS) protection circuits are presented. Bilateral latch-up self-triggering resulting from serial resistance or serial inductance on V-dd or V-ss is discussed. Optimizing the layout and design of output buffers to improve product performance and reliability is also recommended. The studies on the behavior of bilateral latch-up in CMOS protection circuits are increasingly important since low-power applications are the future trend.
URI: http://dx.doi.org/10.1143/JJAP.33.75
http://hdl.handle.net/11536/2715
ISSN: 0021-4922
DOI: 10.1143/JJAP.33.75
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
Volume: 33
Issue: 1A
起始頁: 75
結束頁: 77
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  1. A1994MV67700014.pdf