|標題:||A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator|
Department of Electronics Engineering and Institute of Electronics
|關鍵字:||CMOS technology;double-quadrature architecture;IEEE 802.11a;low-noise amplifier;quadrature generator;quadrature voltage-controlled oscillator;radio frequency;receiver|
|摘要:||A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 mum CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.|
|期刊:||IEEE JOURNAL OF SOLID-STATE CIRCUITS|
|Appears in Collections:||Articles|
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