標題: A maskable memory architecture for rank-order filtering
作者: Dung, LR
Lin, MC
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: rank-order filter;image processing;VLSI architecture;maskable memory;median filter
公開日期: 1-May-2004
摘要: This paper presents a novel implementation Of rank-order filtering using maskable memory. Based on a generic bit-sliced rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank order filtering, threshold decomposition and polarization. In conventional designs, these operations are usually implemented as logic circuit and require complex computation. Using the memory-oriented architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read partial write, and pipelined processing. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits,for parallel read/write operations. Combining the bit-sliced read with polarization selector allows PMM to perform polar determination while the partial write achieves polarization. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in term -3 of cost and speed(I).
URI: http://dx.doi.org/10.1109/TCE.2004.1309423
http://hdl.handle.net/11536/26845
ISSN: 0098-3063
DOI: 10.1109/TCE.2004.1309423
期刊: IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
Volume: 50
Issue: 2
起始頁: 558
結束頁: 564
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