標題: MR: A new framework for multilevel full-chip routing
作者: Chang, YW
Lin, SP
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: detailed routing;estimation;global routing;layout;physical design;routing;timing optimization
公開日期: 1-May-2004
摘要: In this paper, we propose a novel framework for multilevel full-chip routing considering both routability and performance called MR. The two-stage multilevel framework consists of coarsening, followed by uncoarsening. Unlike the previous multilevel routing, MR integrates global routing, detailed routing, and resource estimation, together at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. Further, the exact routing information obtained at each level makes MR more flexible in dealing with various routing objectives (such as crosstalk, power, etc.). Experimental results show that MR obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, MR achieves 100% routing completion for all circuits, while the previous multilevel routing, the three-level routing, and the hierarchical routing can complete routing for only 2, 0, 2 circuits, respectively. In particular, the number of routing layers used by MR is even smaller. We also have performed experiments on timing-driven routing. The results are also very promising.
URI: http://dx.doi.org/10.1109/TCAD.2004.826547
http://hdl.handle.net/11536/26818
ISSN: 0278-0070
DOI: 10.1109/TCAD.2004.826547
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 23
Issue: 5
起始頁: 793
結束頁: 800
Appears in Collections:Conferences Paper


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