標題: Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode
作者: Zhu, SY
Yu, HY
Chen, JD
Whang, SJ
Chen, JH
Shen, C
Zhu, CX
Lee, SJ
Li, MF
Chan, DSH
Yoo, WJ
Du, AY
Tung, CH
Singh, J
Chin, A
Kwong, DL
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Oct-2004
摘要: Both P- and N-channel MOSFET's with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420degreesC. PMOSFETs with PtSi S/D show excellent electrical performance of an I-on/I-off similar to 10(7)-10(8) and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have similar to3 orders of magnitude larger I-off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I-on/I-off similar to 10(5) at low drain voltage. It can be attributed to the relatively higher barrier height (Phi(n)) of DySi2-x/n-Si than that of PtSi/p-Si (Phi(p)) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (similar to1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed. (C) 2004 Published by Elsevier Ltd.
URI: http://dx.doi.org/10.1016/j.sse.2004.05.045
http://hdl.handle.net/11536/26327
ISSN: 0038-1101
DOI: 10.1016/j.sse.2004.05.045
期刊: SOLID-STATE ELECTRONICS
Volume: 48
Issue: 10-11
起始頁: 1987
結束頁: 1992
Appears in Collections:Conferences Paper


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