標題: SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process
作者: Ker, MD
Chen, ZP
電機學院
College of Electrical and Computer Engineering
關鍵字: electrostatic discharge (ESD);holding voltage;latch-up;silicon-controlled rectifier (SCR)
公開日期: 1-Oct-2004
摘要: A dynamic-holding-voltage silicon-controlled rectifier (DHVSCR) device is proposed and verified in a 0.25-mum/2.5-V salicided CMOS process. In the DHVSCR device structure, the control nMOS and pMOS transistors are directly embedded in SCR device structure. The proposed DHVSCR device has the characteristics of tunable holding voltage and holding current by changing the gate voltage of embedded nMOS and pMOS. Under normal circuit operating condition, the DHVSCR has a holding voltage higher than the supply voltage without causing a latch-up issue. Under an electrostatic discharge (ESD) stress condition, the DHVSCR has a lower holding voltage to effectively clamp the overshooting ESD voltage. From the experimental results, the DHVSCR with a device width of 50 mum can sustain a human-body-model ESD level of 5.6 kV.
URI: http://dx.doi.org/10.1109/TED.2004.834904
http://hdl.handle.net/11536/26326
ISSN: 0018-9383
DOI: 10.1109/TED.2004.834904
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 51
Issue: 10
起始頁: 1731
結束頁: 1733
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