標題: Linear low voltage nano-scale CMOS transconductor
作者: Lo, Tien-Yu
Hung, Chung-Chih
Lo, Chi-Hsiang
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: Transconductor;Subthreshold;THD
公開日期: 1-一月-2011
摘要: This paper presents a high linearity MOSFET-only transconductor based on differential structures. While a precise BSIM4 transistor model is introduced through analysis, the linearity can be improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. When the compensation utilizes transistors in subthreshold region, rather than the transistors in saturation region, the value of transconductance can be maintained. The circuit is fabricated in TSMC 0.18-mu m CMOS process. The measurement results show 18 dB improvement of the proposed version, and 65 dB HD3 can be achieved for a 2.1 MHz 700 mV(pp) differential input. The static power consumption under 1-V power supply voltage is 183 mu W. Measurement results demonstrate the agreement with theoretical analyses.
URI: http://dx.doi.org/10.1007/s10470-010-9520-6
http://hdl.handle.net/11536/26034
ISSN: 0925-1030
DOI: 10.1007/s10470-010-9520-6
期刊: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume: 66
Issue: 1
起始頁: 1
結束頁: 7
顯示於類別:期刊論文


文件中的檔案:

  1. 000286933900001.pdf