標題: Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain
作者: Lu, Yi-Hsien
Kuo, Po-Yi
Wu, Yi-Hong
Chen, Yi-Hsuan
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
關鍵字: Gate-all-around (GAA);nanowire (NW);poly-Si thin-film transistors (poly-Si TFTs);raised source/drain (S/D)
公開日期: 1-二月-2011
摘要: We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7 x 12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing similar to 99 mV/dec, and high I(ON)/I(OFF) > 10(7) (V(D) = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.
URI: http://dx.doi.org/10.1109/LED.2010.2093557
http://hdl.handle.net/11536/25819
ISSN: 0741-3106
DOI: 10.1109/LED.2010.2093557
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 32
Issue: 2
起始頁: 173
結束頁: 175
顯示於類別:期刊論文


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  1. 000286677700021.pdf