標題: Substrate Pick-Up Impacting on ESD Performances of Cascode NMOS Transistors
作者: Huang, Shao-Chang
Chen, Ke-Horng
電機工程學系
電控工程研究所
Department of Electrical and Computer Engineering
Institute of Electrical and Control Engineering
關鍵字: ESD
公開日期: 1-二月-2011
摘要: The cascode NMOS architecture has been tested by the Human Body Model (HBM), Machine Model (MM) and Transmission Line Pulse Generator (TLP) in this paper. For the TLP, detailed silicon data have been analyzed well in many parameters, such as the first triggering-on voltage (Vt1), the first triggering-on current (It1), the holding voltage (Vh), and the TLP I-V curve. Besides the above three kinds of Electrostatic Discharge (ESD) events, the device gate oxide breakdown voltage is also taken into consideration and the correlations between HBM, MM and TLP are also observed. In order to explain the bipolar transistor turning-on mechanisms, two kinds of models have been proposed in this paper. In typical cases, substrate resistance decreases as the technology advances. On the one hand, for processes older than the 0.35 mu m process, such as 0.5 mu m and 1 mu m, ESD designers can use pick-up insertions to trigger integrated circuits (IC) turn on uniformly. The NPN Side Model can dominate ESD performances in such old processes. On the other hand, in 0.18 mu m and newer processes, such as 0.15 mu m, 0.13 mu m, 90 nm, etc., ESD designers must use non-pick-up insertion structures. The NPN Central Model can dominate ESD performances in such processes. After combining both models together, the bipolar turning-on mechanisms can be explained as "ESD currents occur from side regions to central regions." Besides ESD parasitic bipolar transistor turning-on concerns, another reason that ESD designers should use non-pick-up insertions in deep sub-micron processes is the decreasing of the gate oxide breakdown voltage. As IC size scales down, the gate oxide thickness lessens. The thinner gate oxide thickness will encounter a smaller gate oxide breakdown voltage. In order to avoid gate oxide damage under ESD stresses, ESD designers should endeavor to decrease ESD device turn-on resistances. ESD protecting devices with low tum-on resistances can endure larger currents for the same TLP voltage. In this paper, silicon data show that the non-pick-up insertion cascode NMOS transistor's turning on resistance is smaller than the pick-up insertion cascode NMOS transistor's turning on resistance. Although this paper discovers NPN turning-on mechanisms based on the cascode NMOS structure, ESD designers can adopt the same theories for other kinds of ESD protecting structures, such as one single poly Gate-Grounded NMOS transistor (GGNMOST). ESD designers can use pick-up insertion architecture for NMOS transistors in the low-end processes, but utilize the non-pick-up insertion architecture for GGNMOST in the high-end processes. Then they can obtain the optimized ESD performances.
URI: http://dx.doi.org/10.1587/transfun.E94.A.688
http://hdl.handle.net/11536/25779
ISSN: 0916-8508
DOI: 10.1587/transfun.E94.A.688
期刊: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Volume: E94A
Issue: 2
起始頁: 688
結束頁: 695
顯示於類別:期刊論文


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