標題: Optimization of back side cleaning process to eliminate copper contamination
作者: Chou, WY
Tsui, BY
Kuo, CW
Kang, TK
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: Copper (Cu) contamination at the wafer bevel, back side surface, and exclusion zone is identified step-by-step following a typical dual-damascene process. The shield ring of a physical vapor deposition system does not protect the exclusion zone and bevel efficiently. Also, Cu may dissolve and accumulate in the solvent used for post dielectric etch clean. Dissolved Cu atoms may then redeposit on the wafer surface. Furthermore, the rough back side surface traps Cu atoms easier than the smooth front side surface. If there is no SiO2 film on the back side surface, post chemical mechanical polish cleaning using dilute HF cannot remove Cu at the back side surface. An optimized single-wafer spin-etch process was proposed. An optimal etchant consisting of HF, HNO3, H2SO4, and H3PO4 with ratios 0.5 :3 :1 :0.5 showed excellent performance. Experiments demonstrated that a very short, 10 s, back side clean can totally remove Cu from back side surface, bevel, and 2 mm exclusion zone. A "wafer shift" procedure was also proposed to solve the pinmark issue near the edge pin due to etchant remnant. The optimized cleaning technique shows shorter process time and higher cleaning efficiency than those reported previously. (C) 2005 The Electrochemical Society.
URI: http://hdl.handle.net/11536/25526
http://dx.doi.org/10.1149/1.1850381
ISSN: 0013-4651
DOI: 10.1149/1.1850381
期刊: JOURNAL OF THE ELECTROCHEMICAL SOCIETY
Volume: 152
Issue: 2
起始頁: G131
結束頁: G137
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