標題: Reducing AC power consumption by three-dimensional integration of Ge-on-insulator CMOS on 1-poly-6-metal 0.18 mu m Si MOSFETs
作者: Yu, DS
Liao, CC
Chen, CC
Lee, CF
Cheng, CF
Chin, A
McAlister, SP
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: We have used three-dimensional (3D) integration to reduce the ac power consumption in interconnects, which is the most severe issue beyond the dc power arising from the gate dielectric leakage current. From a direct calculation of the ac power consumption using an electromagnetic method, we show that both the ac power consumption and maximum operation frequency can be improved by integrating an additional integrated circuit layer. The 3D integration was realized by Ge-on-insulator (GOI) complementary metal oxide semiconductor field effect transistors (CMOSFETs) on 1-poly-6-metal (1P6M) 0.18 mu m Si devices, where little performance degradation was measured in the lower layer 0.18 mu m Si MOSFETs, due to the inherent low thermal budget (500 degrees C rapid thermal anneal) of the GOI processing. The drive current of the 3D GOI n- and p-MOSFETs was more than double that of the control Si devices, providing another advantage of the approach. (c) 2005 The Electrochemical Society. All rights reserved.
URI: http://hdl.handle.net/11536/25441
http://dx.doi.org/10.1149/1.1949088
ISSN: 0013-4651
DOI: 10.1149/1.1949088
期刊: JOURNAL OF THE ELECTROCHEMICAL SOCIETY
Volume: 152
Issue: 8
起始頁: G684
結束頁: G687
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