標題: 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
作者: Chiu, Yi-Wei
Hu, Yu-Hao
Tu, Ming-Hsien
Zhao, Jun-Kai
Chu, Yuan-Hua
Jou, Shyh-Jye
Chuang, Ching-Te
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
關鍵字: Data-aware;low supply voltage;SRAM;subthreshold voltage;write-assist
公開日期: 1-九月-2014
摘要: This paper presents a new bit-interleaving 12T sub-threshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical V-DD to 350 mV (similar to 100 mV lower than the threshold voltage) with V-DDMIN limited by Read operation. Data can be written successfully for V-DD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 mu W at 350 mV, 25 degrees C.
URI: http://dx.doi.org/10.1109/TCSI.2014.2332267
http://hdl.handle.net/11536/25204
ISSN: 1549-8328
DOI: 10.1109/TCSI.2014.2332267
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 61
Issue: 9
起始頁: 2578
結束頁: 2585
顯示於類別:期刊論文


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  1. 000341593700007.pdf