標題: NEW DESIGN METHODOLOGY AND NEW DIFFERENTIAL LOGIC-CIRCUITS FOR THE IMPLEMENTATION OF TERNARY LOGIC SYSTEMS IN CMOS-VLSI WITHOUT PROCESS MODIFICATION
作者: HUANG, HY
WU, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: TERNARY LOGIC SYSTEM;CMOS DYNAMIC LOGIC CIRCUIT;BINARY-CODED TERNARY SIGNAL;REDUNDANT BINARY ADDER
公開日期: 1-Jun-1994
摘要: A new design methodology is proposed and analyzed for the design of ternary logic systems. In the new ternary logic systems, no conversions among radices are required and only the two-state ternary literals associated with the ternary signals are transmitted in the whole system. With the new design methodology, the ternary systems can be realized by the dynamic CMOS logic circuits which are simple and fully compatible with those of the conventional binary logic circuits in process, power supply, and logic levels. A new dynamic differential logic called the CMOS Redundant Differential Logic (CRDL) is also developed to increase the logic flexibility and the circuit performance. Using the new design methodology and the CRDL circuits, the multiplier with redundant binary addition tree is designed in both non-pipelined and pipelined systems. The experimental chip has been fabricated and measured, which successfully verifies the correctness of the logic functions and the speed performance of the designed circuits.
URI: http://hdl.handle.net/11536/2476
ISSN: 0916-8524
期刊: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E77C
Issue: 6
起始頁: 960
結束頁: 969
Appears in Collections:Articles