Title: Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function
Authors: Liu, Sean Shih-Ying
Luo, Ren-Guo
Aroonsantidecha, Suradeth
Chin, Ching-Yu
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: Design for manufacture;design for quality;design methodology;electronic design automation;logic design;placement;temperature control;thermal analysis
Issue Date: 1-Jun-2014
Abstract: In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240x speedup.
URI: http://dx.doi.org/10.1109/TVLSI.2013.2268582
http://hdl.handle.net/11536/24693
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2013.2268582
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 22
Issue: 6
Begin Page: 1404
End Page: 1415
Appears in Collections:Articles


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