標題: Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function
作者: Liu, Sean Shih-Ying
Luo, Ren-Guo
Aroonsantidecha, Suradeth
Chin, Ching-Yu
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Design for manufacture;design for quality;design methodology;electronic design automation;logic design;placement;temperature control;thermal analysis
公開日期: 1-六月-2014
摘要: In this paper, we present a fast and accurate thermal aware analytical placer. A thermal model is constructed based on a Green function with discrete cosine transform (DCT) to generate full chip temperature profile. Our thermal model is tightly integrated with an analytical placer implemented based on the SimPL framework. A temperature spreading force based on the Gaussian model is proposed to reduce the maximum on-chip temperature and optimize tradeoff between total half-perimeter wirelength and on-chip maximum temperature. The temperature profile generated using our thermal model is verified by the ANSYS ICEPAK and obtains an average deviation within 3.0% with 240x speedup.
URI: http://dx.doi.org/10.1109/TVLSI.2013.2268582
http://hdl.handle.net/11536/24693
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2013.2268582
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 22
Issue: 6
起始頁: 1404
結束頁: 1415
顯示於類別:期刊論文


文件中的檔案:

  1. 000337167600018.pdf