標題: Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs
作者: Lin, Chen-Wei
Chao, Mango C. -T.
Hsu, Chih-Chieh
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Defect modeling;gate-oxide short;SRAM;testing
公開日期: 1-六月-2014
摘要: Gate oxide short (GOS) has become a common defect for advanced technologies as the gate oxide thickness of a MOSFET is greatly reduced. The behavior of a GOS-impacted MOSFET is, however, complicated and difficult to be accurately modeled at the circuit level. In this paper, we first build a golden model of a GOS-impacted MOSFET by using technology CAD, and identify the limitation and inaccuracy of the previous GOS models. Next, we propose a novel circuit-level GOS model which provides a higher accuracy of its dc characteristics than any of the previous models and being is able to represent a minimum-size GOS-impacted MOSFET. In addition, the proposed model can fit the transient characteristics of a GOS by considering the capacitance change of the GOS-impacted MOSFET, which has not been discussed in previous work. Last, we utilize our proposed GOS model to develop a novel GOS test method for SRAMs, which can effectively detect the GOS defects usually escaped from the conventional IDDQ test and March test.
URI: http://dx.doi.org/10.1109/TVLSI.2013.2268984
http://hdl.handle.net/11536/24692
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2013.2268984
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 22
Issue: 6
起始頁: 1294
結束頁: 1307
顯示於類別:期刊論文


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