Title: Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection
Authors: Lin, Chun-Yu
Fan, Mei-Lian
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: Diode;electrostatic discharge (ESD);layout;stackup
Issue Date: 1-Jun-2014
Abstract: The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V-DD or lower than V-SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.
URI: http://dx.doi.org/10.1109/TDMR.2014.2311130
http://hdl.handle.net/11536/24688
ISSN: 1530-4388
DOI: 10.1109/TDMR.2014.2311130
Journal: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 14
Issue: 2
Begin Page: 775
End Page: 777
Appears in Collections:Articles


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