標題: Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices
作者: Hsiao, Yi-Hsuan
Lue, Hang-Ting
Chen, Wei-Chen
Chang, Kuo-Pin
Shih, Yen-Hao
Tsui, Bing-Yue
Hsieh, Kuang-Yeu
Lu, Chih-Yuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 3-D NAND Flash;grain boundary;grain boundary traps;poly Si thin-film transistor (TFT);vertical gate (VG)
公開日期: 1-六月-2014
摘要: The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.
URI: http://dx.doi.org/10.1109/TED.2014.2318716
http://hdl.handle.net/11536/24661
ISSN: 0018-9383
DOI: 10.1109/TED.2014.2318716
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 61
Issue: 6
起始頁: 2064
結束頁: 2070
顯示於類別:期刊論文


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