標題: A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
作者: Lin, Mu-Shan
Tsai, Chien-Chun
Chang, Chih-Hsien
Huang, Wen-Hung
Hsu, Ying-Yu
Yang, Shu-Chun
Fu, Chin-Ming
Chou, Mao-Hsuan
Huang, Tien-Chien
Chen, Ching-Fang
Huang, Tze-Chiang
Adham, Saman
Wang, Min-Jer
Shen, William Wu
Mehta, Ashok
交大名義發表
National Chiao Tung University
關鍵字: Chip on wafer on substrate;CoWoS;DLL;eDRAM;low-swing IO;micro-bump;PHY;PLL;SII;silicon-interposer;timing compensation;2.5D-IC.
公開日期: 1-四月-2014
摘要: A 1 Tbit/ s bandwidth PHY is demonstrated through CoWoS(TM) platform. Two chips: SOC and embedded DRAM ( eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/ s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low- power and small area eDRAM PHY that excludes PLL/ DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low- swing IO also achieves power efficiency of 0.105 mW/ Gbps.
URI: http://dx.doi.org/10.1109/JSSC.2013.2297399
http://hdl.handle.net/11536/24264
ISSN: 0018-9200
DOI: 10.1109/JSSC.2013.2297399
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 49
Issue: 4
起始頁: 1063
結束頁: 1074
顯示於類別:期刊論文


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  1. 000334114600024.pdf