標題: A low-glitch binary-weighted DAC with delay compensation scheme
作者: Chou, Fang-Ting
Chen, Chia-Min
Hung, Chung-Chih
資訊工程學系
Department of Computer Science
關鍵字: Digital-to-analog converter (DAC);Glitch reduction;Binary-weighted;Current-steering DAC
公開日期: 1-五月-2014
摘要: This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Omega termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 mu m CMOS technology and dissipates 19 mW from a single 1.8 V power supply.
URI: http://dx.doi.org/10.1007/s10470-014-0262-8
http://hdl.handle.net/11536/24217
ISSN: 0925-1030
DOI: 10.1007/s10470-014-0262-8
期刊: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume: 79
Issue: 2
起始頁: 277
結束頁: 289
顯示於類別:期刊論文


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  1. 000333611000009.pdf